The invention relates generally to a method for making a semiconductor device, for example, a method of forming contact holes in a nonvolatile memory array.
One prior art process using a hard mask stack, as shown in FIG. 1, can be used to fabricate 45 nm and 80 nm features. The stack consists of a layer of organic hard mask 103, also known as an amorphous carbon advanced patterning film (APF), a layer of Dielectric Anti-Reflective Coating (DARC) 106, such as silicon oxynitride, on top of organic hard mask 103, and a Bottom Anti-Refection Coating (BARC) 109 layer, such as an organic BARC layer, on top of DARC layer 106. A photoresist 111 can be coated above the BARC layer. A device layer 110 can be etched using at least one or more layers of the stack as a mask.
In conventional patterning, such as double printing, resolution below 38 nanometers is not achievable. Alternate technologies for approaching 24 nm contact hole resolution is very difficult and involves the use of 2-row staggered arrays. To perform even smaller hole patterning, such as below 22 nm, 3-row staggered arrays may be required resulting in additional difficulties, such as increased reliance on optical proximity correction and sub-resolution assist features.